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PRELIMINARY DATA SHEET
128M bits Mobile RAM
EDL1216CFBJ (8M words x 16 bits)
Specifications
* Density: 128M bits * Organization: 2M words x 16 bits x 4 banks * Package: 60-ball FBGA Lead-free (RoHS compliant) and Halogen-free * Power supply: VDD, VDDQ = 1.7V to 1.95V * Clock frequency: 133MHz (max.) * 1KB page size Row address: A0 to A11 Column address: A0 to A8 * Four internal banks for concurrent operation * Interface: LVCMOS * Burst lengths (BL): 1, 2, 4, 8, full page * Burst type (BT): Sequential (1, 2, 4, 8, full page) Interleave (1, 2, 4, 8) * /CAS Latency (CL): 3 * Precharge: auto precharge option for each burst access * Driver strength: normal/weak * Refresh: auto-refresh, self-refresh * Refresh cycles: 4096 cycles/64ms Average refresh period: 15.6s * Operating ambient temperature range TA = -25C to +85C
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
1
2
3
4
5
6
7
8
9
10
A
VSS DQ15 VSSQ
VDDQ DQ0 VDD
DQ1 DQ2 VSSQ
DQ3 DQ4 VDDQ
DQ5 DQ6 VSSQ
DQ7
NC NC
B
VDDQ DQ13 DQ14
C
VSSQ DQ11 DQ12
D
VDDQ DQ9 DQ10
E
NC NC
DQ8
F
VSS UDQM NC
NC LDQM VDD
G
CKE CLK
NC
/WE /CAS /RAS
/CS
H
A9
A11
A7
A4
NC
A8
A5
BA0
BA1
A1
VDD
J
A6
A10/AP A0
K
VSS
A2
A3
(Top view) A0 to A11 BA0, BA1 DQ0 to DQ15 CLK CKE /CS /RAS /CAS /WE UDQM LDQM VDD VSS VDDQ VSSQ NC Address inputs Bank select Data inputs/ outputs Clock input Clock enable Chip select Row address strobe Column address strobe Write enable Upper DQ mask enable Lower DQ mask enable Power supply Ground Power supply for DQ Ground for DQ No connection
Features
* * * * * * Low power consumption Single pulsed /RAS Burst read/write operation capability Byte control by DQM Programmable Partial Array Self-Refresh Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor * Burst termination by burst stop command and Precharge command
Document No. E1137E51 (Ver. 5.1) Date Published August 2008 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2007-2008
EDL1216CFBJ
Ordering Information
Part number EDL1216CFBJ-75-F Organization (words x bits) 8M x 16 Internal banks 4 Clock frequency MHz (max.) 133 /CAS latency 3 Package 60-ball FBGA
Part Number
E D L 12 16 C F BJ - 75 - F
Elpida Memory
Type D: Monolithic Device
Environment Code F: Lead Free (RoHS compliant)
and Halogen Free
Speed 75: 133MHz/CL3
Product Family L: SDR Mobile RAM
Density 12: 128M Organization 16: x16 Power Supply, Interface C: VDD = 1.8V, VDDQ = 1.8V, LVCMOS
Package BJ: FBGA
Die Rev.
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Pin Configurations .........................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Electrical Specifications.................................................................................................................................4 Pin Function...................................................................................................................................................9 Command Operation ...................................................................................................................................11 Truth Table ..................................................................................................................................................15 Simplified State Diagram .............................................................................................................................20 Initialization ..................................................................................................................................................21 Programming Mode Registers.....................................................................................................................21 Address Bits of Bank-Select and Precharge ...............................................................................................25 Operation of the Mobile RAM ......................................................................................................................26 Timing Waveforms.......................................................................................................................................34 Package Drawing ........................................................................................................................................56 Recommended Soldering Conditions..........................................................................................................57
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 200 s and then, execute Power on sequence and two Auto Refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD, VDDQ IOS PD TA Tstg Rating -0.5 to +2.45 -0.5 to +2.45 50 1.0 -25 to +85 -55 to +125 Unit V V mA W C C Note
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = -25C to +85C)
Parameter Supply voltage DQ Supply voltage Input high voltage Input low voltage Symbol VDD VSS, VSSQ VDDQ VIH VIL min. 1.7 0 1.7 0.8 x VDDQ -0.3 typ. 1.8 0 1.8 max. 1.95 0 1.95 VDDQ + 0.3 0.3 Unit V V V V V 1 2 Notes
Notes: 1. VIH (max.) = 2.45V (pulse width 5ns) 2. VIL (min.) = -0.5V (pulse width 5ns)
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
DC Characteristics 1 (TA = -25C to +85C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter /CAS latency Operating current Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Symbol IDD0 IDD2P IDD2PS Grade max. 40 0.8 0.6 Unit mA mA mA Test condition Burst length = 1 tRC tRC (min.), IO = 0mA, One bank active CKE VIL (max.), tCK (min.) CKE VIL (max.), tCK = CKE VIH (min.), tCK (min.), /CS VIH (min.), Input signals are changed one time during 2tCK. CKE VIH (min.), tCK = , Address and Command Input signals are stable. CKE VIL (max.), tCK (min.) CKE VIL (max.), tCK = CKE VIH (min.), tCK (min.), /CS VIH (min.), Input signals are changed one time during 2tCK. CKE VIH (min.), tCK = , Address and Command Input signals are stable. tCK tCK (min.), IOUT = 0mA, All banks active tRC1 tRC1 (min.) Notes
IDD2N
4.0
mA
Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) Burst operating current Refresh current
IDD2NS IDD3P IDD3PS
2.0 3.0 2.0
mA mA mA
IDD3N
10
mA
IDD3NS IDD4 IDD5
7.0 80 70
mA mA mA
1 2
Self Refresh Current (TA = -25C to +85C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Self refresh current PASR="000" (Full) PASR="001" (2BK) PASR="010" (1BK) PASR="000" (Full) PASR="001" (2BK) PASR="010" (1BK) IDD6 Symbol IDD6 Grade typ. max. 140 120 110 210 160 140 Unit A A A A A A +45C < TA 85C CKE 0.2V 3 Test Condition -25C TA +45C CKE 0.2V Notes 3
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Notes: 1. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD4 is measured on condition that addresses are changed only one time during tCK (min.). 2. IDD5 is measured on condition that addresses are changed only one time during tCK (min.). 3. IDD6 is specified when self refresh state is maintained long enough under the specified TA condition, after a busy sequence of read and write operations
DC Characteristics 2 (TA = -25C to +85C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. -2.0 -1.5 VDDQ - 0.2 -- max. 2.0 1.5 -- 0.2 Unit A A V V Test condition 0 VIN VDDQ 0 VOUT VDDQ, DQ = disable IOH = -0.1 mA IOL = 0.1 mA Notes
Pin Capacitance (TA = 25C, f = 1MHz)
Parameter Input capacitance Data input/output capacitance Symbol CI1 CI2 CI/O Pins CLK All other input-only pins DQ min. 1.5 1.5 2.0 typ. -- -- -- max. 3.5 3.0 4.5 Unit pF pF pF Notes
AC Characteristics (TA = -25C to +85C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V) Test Conditions * AC high level input voltage / low level input voltage: 1.6 / 0.2V * Input timing measurement reference level: 0.9V * Transition time (Input rise and fall time): 0.5ns * Output timing measurement reference level: 0.9V * Output load: CL = 30pF
tCK
tCH
CLK 1.6 V 0.9 V 0.2 V
tSETUP tHOLD
tCL
Input
1.6 V 0.9 V 0.2 V
tAC
tOH
I/O CL
Output
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Synchronous Characteristics
Parameter Clock cycle time (CL= 2) (CL= 3) Access time from CLK (CL= 2) (CL= 3) CLK high level width CLK low level width Data-out hold time Data-out low-impedance time Data-out high-impedance time (CL= 2) (CL= 3) Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time CKE setup time (Power down exit) Command (/CS, /RAS, /CAS, /WE, UDQM/LDQM) setup time Command (/CS, /RAS, /CAS, /WE, UDQM/LDQM) hold time Symbol tCK2 tCK3 tAC2 tAC3 tCH tCL tOH tLZ tHZ2 tHZ3 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS tCMH min. 15 7.5 -- -- 2.5 2.5 2.5 1 0 0 1.9 0.9 1.9 0.9 1.9 0.9 1.9 1.9 0.9 max. 100 100 8 5.4 -- -- -- -- 8 5.4 -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 Note
Note: 1. Output load.: CL = 30pF
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Asynchronous Characteristics
Parameter Symbol min. 75 77 112.5 52.5 22.5 30 2 2 2CLK + 22.5 2CLK + 22.5 2 0.5 1CLK + tCKSP 1 1 1 max. 120000 Unit ns ns ns ns ns ns CLK CLK ns ns CLK ns ms tCK CLK CLK CLK Notes ACT to REF/ACT command period (operation) tRC REF to REF/ACT command period Self refresh exit to REF/ACT command period ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT (one) to ACT (another) command period Data-in to PRE command period Data-in to ACT (REF) command period (Auto precharge) (CL = 2) (CL = 3) Mode register set cycle time Transition time Refresh time (4,096 refresh cycles) Power down exit time Last data in to burst stop Last data-in to new column address delay Column address to column address delay tRC1 tRC2 tRAS tRP tRCD tRRD tDPL tDAL2 tDAL3 tRSC tT tREF tPDEX tBDL tCDL tCCD

30 64
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Pin Function
CLK (input pin) CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE (input pins) CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Mobile RAM suspends operation. When the Mobile RAM is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. /CS (input pins) /CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. A0 to A11 (input pins) Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle. It does not depend on the bit organization. Column Address (See "Address Pins Table") is determined by A0 to A8 at the CLK rising edge in the read or write command cycle. [Address Pins Table]
Address (A0 to A11) Part number EDL1216CFBJ Row address AX0 to AX11 Column address AY0 to AY8
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by BA0 and BA1 is precharged. When A10 is high in read or write command cycle, the precharge starts automatically after the burst access. BA0 and BA1 (input pin) BA0 and BA1 are bank select signal. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank A Bank B Bank C Bank D L H L H BA1 L L H H
Remark: H: VIH. L: VIL.
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
UDQM to LDQM (input pins) UDQM and LDQM control upper byte and lower byte I/O buffers, respectively. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 to DQ15 (input/output pins) DQ pins have the same function as I/O pins on a conventional DRAM. VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers.
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Command Operation
Extended Mode register set command (/CS, /RAS, /CAS, /WE, BA0 = Low, BA1 = High) The Mobile RAM has an extended mode register that defines low power functions. In this command, A0 through A11 are the data input pins. After power on, the extended mode register set command must be executed to fix low power functions. The extended mode register can be set only when all banks are in idle state. During tRSC following this command, the Mobile RAM can not accept any other commands.
CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 Add H
Extended Mode register set command Mode register set command (/CS, /RAS, /CAS, /WE, BA0, BA1 = Low) The Mobile RAM has a mode register that defines how the device operates. In this command, A0 through A11 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During tRSC following this command, the Mobile RAM cannot accept any other commands.
CLK CKE /CS /RAS /CAS /WE
BA0
BA1
H
A10 Add
Mode register set command Activate command (/CS, /RAS = Low, /CAS, /WE = High) The Mobile RAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0 and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's /RAS falling.
CLK CKE /CS /RAS /CAS /WE
BA0, BA1 A10 Add
Row Row
H
Activate command
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Precharge command (/CS, /RAS, /WE = Low, /CAS = High) This command begins precharge operation of the bank selected by BA0 and BA1. When A10 is High, all banks are precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged. After this command, the Mobile RAM can't accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM's /RAS rising.
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10
(Precharge select)
H
Add
Precharge command Write command (/CS, /CAS, /WE = Low, /RAS = High) This command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clocks.
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add Col. H
Write command Read command (/CS, /CAS = Low, /RAS, /WE = High) Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column address.
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add Col. H
Read command
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Auto refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) This command is a request to begin the Auto refresh operation. The refresh address is generated internally. Before executing Auto refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC1 period (from refresh command to refresh or activate command), the Mobile RAM cannot accept any other command
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add H
Auto refresh command Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the Mobile RAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged.
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add
Self refresh entry command Power down entry command (/CS, CKE = Low, /RAS, /CAS, /WE = High) After the command execution, power down mode continues while CKE remains low. When CKE goes high, the Mobile RAM exits the power down mode. Before executing power down, all banks must be precharged.
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add
Power down entry command
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Burst stop command (/CS = /WE = Low, /RAS, /CAS = High) This command can stop the current burst operation.
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add H
Burst stop command No operation (/CS = Low, /RAS, /CAS, /WE = High) This command is not an execution command. No operations begin or terminate by this command.
CLK CKE /CS /RAS /CAS /WE BA0, BA1 A10 Add H
No operation
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Truth Table
Command Truth Table
CKE Function Device deselect No operation Burst stop Read Read with auto precharge Write Write with auto precharge Bank activate Precharge select bank Precharge all banks Mode register set Extended mode register set Symbol DESL NOP BST READ READA WRIT WRITA ACT PRE PALL MRS EMRS n-1 H H H H H H H H H H H H n x x H x x x x x x x x x /CS H L L L L L L L L L L L /RAS x H H H H H H L L L L L /CAS x H H L L L L H H H L L /WE x H L H H L L H L L L L BA1 x x x V V V V V V x L H BA0 x x x V V V V V V x L L A10 x x x L H L H V L H L L A11, A9 - A0 x x x V V V V V x x V V
Remark: H: VIH. L: VIL. x: Don't care, V = Valid data DQM Truth Table
CKE Function Data write / output enable Data mask / output disable Upper byte write enable / output enable Lower byte write enable / output enable Upper byte write inhibit / output disable Lower byte write inhibit / output disable Symbol ENB MASK ENBU ENBL MASKU MASKL n-1 H H H H H H n x x x x x x DQM U L H L x H x L L H x L x H
Remark: H: VIH. L: VIL. x: Don't care CKE Truth Table
CKE Current state Activating Any Clock suspend Idle Idle Idle/Active Self refresh Power down Function Clock suspend mode entry Clock suspend mode Clock suspend mode exit Auto refresh command Self refresh entry Power down entry Self refresh exit Power down exit REF SELF PD Symbol n-1 H L L H H H H L L L L n L L H H L L L H H H H /CS x x x L L L H L H L H /RAS x x x L L H x H x H x /CAS x x x L L H x H x H x /WE x x x H H H x H x H x Address x x x x x x x x x x x
Remark: H: VIH. L: VIL. x: Don't care
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Function Truth Table
Current state Idle /CS H L L L L L L L L L Row active H L L L L L L L L Read H L L L L L L L L Write H L L L L L L L L /RAS /CAS /WE Address x H H H H L L L L L x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H L H L H L H L L x H L H L H L H L x H L H L H L H L x H L H L H L H L x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA1= L OC, BA1= H x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF MRS EMRS DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS Action Nop Nop Nop ILLEGAL ILLEGAL Row activating Nop Auto refresh Mode register set Extended mode register set Nop Nop Nop Begin read Begin write ILLEGAL Precharge/Precharge all banks ILLEGAL ILLEGAL Continue burst to end Row active Continue burst to end Row active Burst stop Row active Terminate burst, begin new read Terminate burst, begin write ILLEGAL Terminate burst Precharging ILLEGAL ILLEGAL Continue burst to end Write recovering Continue burst to end Write recovering Burst stop Row active Terminate burst, start read : Determine AP Terminate burst, new write : Determine AP ILLEGAL Terminate burst Precharging ILLEGAL ILLEGAL 5, 6 5 2 7 5 5, 6 2 3 3 2 4 2 2 Notes
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Current state Read with auto precharge
/CS H L L L L L L L L
/RAS /CAS /WE Address x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H L H L H L H L x H L H L H L H L x H L H L H L H L x H L H L H L H L x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA
Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS
Action Continue burst to end Precharging Continue burst to end Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Write recovering with auto precharge Continue burst to end Write recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP Nop Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP ILLEGAL ILLEGAL Nop Enter bank active after tRCD Nop Enter bank active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
2 2 2 2
Write with auto precharge
H L L L L L L L L
2 2 2 2
Precharging
H L L L L L L L L
2 2 2
Row activating
H L L L L L L L L
2 2 2, 8 2
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Current state Write recovering /CS H L L L L L L L L Write recovering with auto precharge H L L L L L L L L Refresh H L L L L L L L L Mode register accessing H L L L L L L L L /RAS /CAS /WE Address x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H L H L H L H L x H L H L H L H L x H L H L H L H L x H L H L H L H L x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x OC, BA Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS/EMRS Action Nop Enter row active after tDPL Nop Enter row active after tDPL Nop Enter row active after tDPL Begin read Begin new write ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter precharge after tDPL Nop Enter precharge after tDPL Nop Enter precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRC1 Nop Enter idle after tRC1 Nop Enter idle after tRC1 ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRSC Nop Enter idle after tRSC Nop Enter idle after tRSC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 2, 6 2 2 2 2 6 Notes
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Current state Extended mode register accessing
/CS H L L L L L L L L
/RAS /CAS /WE Address x H H H H L L L L x H H L L H H L L x H L H L H L H L x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF
Action Nop Enter idle after tRSC Nop Enter idle after tRSC Nop Enter idle after tRSC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
OC, BA0,BA1 MRS/EMRS
Remark: H: VIH. L: VIL. x: Don't care, V = Valid data BA: Bank Address, CA: Column Address, RA: Row Address, OC: Op-Code Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H). 2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 3. Illegal if tRCD is not satisfied. 4. Illegal if tRAS is not satisfied. 5. Must satisfy burst interrupt condition. 6. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 7. Must mask preceding data which don't satisfy tDPL. 8. Illegal if tRRD is not satisfied.
Preliminary Data Sheet E1137E51 (Ver. 5.1)
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EDL1216CFBJ
Simplified State Diagram
EXTENDED MODE REGISTER SET
EMRS
SELF REFRESH
SR ENTRY SR EXIT
MODE REGISTER SET
MRS
REFRESH
IDLE
AUTO REFRESH
CKE CKE_
IDLE POWER DOWN
ACTIVE POWER DOWN
CKE_ CKE
ACTIVE
BST
ROW ACTIVE
BST
WRITE
Write
READ WRITE WITH AP READ READ WITH AP READ WITH AP WRITE WRITE WITH AP
Read
WRITE SUSPEND
CKE_
CKE_
WRITE
CKE WRITE WITH AP CKE_
READ
CKE READ WITH AP CKE_
READ SUSPEND
PRECHARGE
WRITEA SUSPEND
WRITEA
CKE PRECHARGE PRECHARGE
READA
CKE
READA SUSPEND
POWER APPLIED
POWER ON
PRECHARGE
PRECHARGE
Automatic sequence Manual input
Preliminary Data Sheet E1137E51 (Ver. 5.1)
20
EDL1216CFBJ
Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, when power is applied, a 200 s or longer pause must precede any signal toggling. VDD should be turned on simultaneously or before VDDQ. (2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks command is convenient). (3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto refresh must be performed. (4) The mode register must be programmed and the extended mode register should be programmed. After the mode register set cycle or the extended mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied. Remarks: 1 The sequence of Auto refresh, mode register programming and extended mode register programming above may be transposed. 2 CKE and DQM must be held high until the Precharge command is issued to ensure data-bus High-Z.
Programming Mode Registers
The mode register and extended mode register are programmed by the Mode register set command and Extended mode register command, respectively using address bits A11 through A0, BA0 and BA1 as data inputs. The registers retain data until they are re-programmed or the device loses power. Mode register The mode register has four fields; Reserved /CAS latency Wrap type Burst length : : : : A11 through A7 A6 through A4 A3 A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed. /CAS Latency /CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. "Burst Length Sequence" shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
Preliminary Data Sheet E1137E51 (Ver. 5.1)
21
EDL1216CFBJ
Extended Mode Register The extended mode register has four fields; Reserved Auto Temperature Compensated Self Refresh Driver Strength Partial Array Self Refresh : A11 through A7, A4, A3 : A9 : A6 through A5 : A2 through A0
Following extended mode register programming, no command can be issued before at least 2 CLK have elapsed. Driver Strength By setting specific parameter on A6 and A5, driving capability of data output drivers is selected. Auto Temperature Compensated Self Refresh (ATCSR) With the built-in temperature sensor, the internal self refresh frequency is controlled autonomously. Partial Array Self Refresh Memory array size to be refreshed during self refresh operation is programmable in order to reduce power. Data outside the defined area will not be retained during self refresh.
Preliminary Data Sheet E1137E51 (Ver. 5.1)
22
EDL1216CFBJ
Mode Register Definition
BA1 BA0
A11
0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
LTMODE
WT
BL
Mode Register Set
Latency mode
Bits6-4 000 001 010 011 100 101 110 111
/CAS latency R R 2 3 R R R R
Burst length
Bits2-0 000 001 010 011 100 101 110 111
0 1
WT = 0 1 2 4 8 R R R Full page
WT = 1 1 2 4 8 R R R R
Wrap type
Sequential Interleave
BA1
BA0 0
A11
0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
0
0
0
DS
0
0
PASR
Extended Mode Register Set
Driver Strength
Bits6-5 00 01 10 11
Strength Normal 1/2 strength 1/4 strength 1/8 strength
Partial Array Self Refresh
Bits2-0 000 001 010 011 100 101 110 111
Refresh Array All banks Bank A & Bank B (BA1=0) Bank A (BA0=BA1=0) R R R R R
Remark R : Reserved
Preliminary Data Sheet E1137E51 (Ver. 5.1)
23
EDL1216CFBJ
Burst Length and Sequence [Burst of Two]
Starting address (column address A0, binary) 0 1 Sequential addressing sequence (decimal) 0, 1 1, 0 Interleave addressing sequence (decimal) 0, 1 1, 0
[Burst of Four]
Starting address (column address A1-A0, binary) 00 01 10 11 Sequential addressing sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave addressing sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
[Burst of Eight]
Starting address (column address A2-A0, binary) 000 001 010 011 100 101 110 111 Sequential addressing sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave addressing sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 512.
Preliminary Data Sheet E1137E51 (Ver. 5.1)
24
EDL1216CFBJ
Address Bits of Bank-Select and Precharge
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
BA0 BA1
BA0 BA1
Result
(Activate command)
0 1 0 1
0 0
1 1
Select Bank A "Activate" command Select Bank B "Activate" command
Select Bank C "Activate" command Select Bank D "Activate" command
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0 BA1
(Precharge command)
A10 0 0 0 0 1
BA0
BA1
0 1 0 1 x
0 0 1 1 x
Result Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks
x : Don't care
0
Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
BA0 BA1
1
disables Auto-Precharge (End of Burst) enables Auto-Precharge (End of Burst)
(/CAS strobes)
BA0 BA1
Result
0 1 0 1
0 0
1 1
enables Read/Write commands for Bank A enables Read/Write commands for Bank B
enables Read/Write commands for Bank C enables Read/Write commands for Bank D
Preliminary Data Sheet E1137E51 (Ver. 5.1)
25
EDL1216CFBJ
Operation of the Mobile RAM
Precharge The precharge command can be issued anytime after tRAS min. is satisfied. Soon after the precharge command is issued, precharge operation performed and the selected bank(s) enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows.
Burst length=4 T0 CLK /CAS latency = 2 Command READ PRE Hi-Z T1 T2 T3 T4 T5 T6 T7 T8
DQ /CAS latency = 3 Command READ
Q1
Q2
Q3
Q4
PRE Hi-Z
DQ
Q1
Q2
Q3
Q4
(tRAS must be satisfied)
Precharge In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL (min.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is calculated by dividing tDPL (min.) with clock cycle time. In summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. /CAS latency 2 3 Read -1 -2 Write +tDPL(min.) +tDPL(min.)
Preliminary Data Sheet E1137E51 (Ver. 5.1)
26
EDL1216CFBJ
Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been satisfied. In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged. The timing that begins the auto precharge cycle depends on whether read or write cycle. Read with Auto Precharge During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS latency of 3) the last data word output.
Burst length = 4 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9
/CAS latency = 2 Command READA B Auto precharge starts
Hi-Z DQ QB1 QB2 QB3 QB4
/CAS latency = 3 Command READA B Auto precharge starts
Hi-Z DQ QB1 QB2 QB3 QB4
(tRAS must be satisfied)
Read with Auto Precharge Remark: READA means Read with Auto precharge Write with Auto Precharge During a write cycle, the auto precharge starts at the timing of 2 clocks after the last data word input to the device.
Burst length = 4 T0 CLK Auto precharge starts T1 T2 T3 T4 T5 T6 T7 T8
Command
WRITA B
Hi-Z DQ DB1 DB2 DB3 DB4
(tRAS must be satisfied)
Write with Auto Precharge Remark: WRITA means Write with Auto Precharge
Preliminary Data Sheet E1137E51 (Ver. 5.1)
27
EDL1216CFBJ
Read / Write Command Interval Read to Read Command Interval During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous read operation does not completed. READ will be interrupted by another READ. The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction.
Burst length = 4, /CAS latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9
Command
READ A
READ B
Hi-Z DQ QA1 QB1 QB2 QB3 QB4
1cycle
Read to Read Command Interval Write to Write Command Interval During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will begin with a new Write command. WRITE will be interrupted by another WRITE. The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock without any restriction.
Burst length = 4 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
WRITE A
WRITE B
Hi-Z DQ DA1 DB1 DB2 DB3 DB4
1cycle
Write to Write Command Interval
Preliminary Data Sheet E1137E51 (Ver. 5.1)
28
EDL1216CFBJ
Write to Read Command Interval Write command and Read command interval is also 1 cycle. Only the write data before Read command will be written. The data bus must be High-Z at least one cycle prior to the first DOUT.
Burst length = 4 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
/CAS latency = 2 Command WRITE A READ B
Hi-Z DQ DA1 QB1 QB2 QB3 QB4
/CAS latency = 3 Command WRITE A READ B
Hi-Z DQ DA1 QB1 QB2 QB3 QB4
Write to Read Command Interval
Preliminary Data Sheet E1137E51 (Ver. 5.1)
29
EDL1216CFBJ
Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data bus must be High-Z using DQM before WRITE.
Burst length = 4 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command DQM
READ
WRITE
Hi-Z DQ 1cycle D1 D2 D3 D4
Read to Write Command Interval 1 READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
Burst length = 8 T0 CLK /CAS latency = 2 Command DQM READ WRITE T1 T2 T3 T4 T5 T6 T7 T8 T9
DQ
Q1
Q2
Q3 Hi-Z is necessary
D1
D2
D3
/CAS latency = 3 Command DQM READ WRITE
DQ
Q1
Q2 Hi-Z is necessary
D1
D2
D3
Read to Write Command Interval 2
Preliminary Data Sheet E1137E51 (Ver. 5.1)
30
EDL1216CFBJ
Burst Termination There are two methods to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command. Burst Termination in READ Cycle During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to High-Z after the /CAS latency from the burst stop command.
Burst length = X T0 CLK T1 T2 T3 T4 T5 T6 T7
Command
READ
BST
/CAS latency = 2 DQ /CAS latency = 3 DQ Q1 Q2 Q3 Q1 Q2 Q3
Hi-Z
Hi-Z
Burst Termination in READ Cycle Remark: BST: Burst stop command Burst Termination in WRITE Cycle During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to High-Z at the same clock with the burst stop command.
Burst length = X T0 CLK T1 T2 T3 T4 T5 T6 T7
Command
WRITE
BST
Hi-Z
DQ
D1
D2
D3
D4
Burst Termination in WRITE Cycle Remark: BST: Burst stop command
Preliminary Data Sheet E1137E51 (Ver. 5.1)
31
EDL1216CFBJ
Precharge Termination in READ Cycle During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Burst length = X, /CAS latency = 2 T0 CLK T1 T2 T3 T4 T5 T6 T7
Command
READ
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
tRP
(tRAS must be satisfied)
Precharge Termination in READ Cycle (CL = 2) When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Burst length = X, /CAS latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
READ
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
tRP
Q4
(tRAS must be satisfied)
Precharge Termination in READ Cycle (CL = 3)
Preliminary Data Sheet E1137E51 (Ver. 5.1)
32
EDL1216CFBJ
Precharge Termination in WRITE Cycle During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. The write data written up to two clocks prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command and one clock before the precharge command. To prevent this from happening, DQM must be high and mask the invalid data.
Burst length = X, /CAS latency = 3 T0 CLK T1 T2 T3 T4 T5 T6 T7 T8
Command
WRITE
PRE
ACT
DQM
Hi-Z
DQ
D1
D2
D3
D4
tDPL
D5
tRP (tRAS must be satisfied)
Precharge Termination in WRITE Cycle
Preliminary Data Sheet E1137E51 (Ver. 5.1)
33
EDL1216CFBJ
; ;;; ;;;; ;;;;;; ;;; ;; ;;;; ;;;; ;;;; ;; ;;;;;;;;; ;;;;;; ; ; ;; ;;;; ;;;; ;;; ;; ;;;;;; ;;;;;;;;;; ;;; ;;; ;;;;;;;;;;;; ;;;; ; ;;; ;;; ; ; ;;;; ;; ;; ;;;
AC Parameters for Read Timing with Manual Precharge
T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK tCH tCL CKE
Timing Waveforms
tCKH
tCKS
tCMS tCMH
/CS
/RAS
/CAS /WE
BA0
BA1
A10
ADD
tAS tAH
DQM DQ
L
tAC
tAC
Hi-Z
tRCD
tLZ
tOH
tRAS
tRC
Activate Command for Bank A
Read Command for Bank A
Precharge Command for Bank A
Preliminary Data Sheet E1137E51 (Ver. 5.1)
34
;;; ;;;
tAC tAC tHZ tOH tOH tOH tRP
Activate Command for Bank A
[Burst Length = 4, /CAS Latency = 3]
EDL1216CFBJ
;;;;;;;;;;;; ;; ;;;;;;;; ;; ;;;;;; ;;; ;;;;; ;;; ;;;;;;;;;; ;;; ;;;;;;;; ;;; ;;;;;; ;;; ;;;; ;;; ;;; ; ; ;;; ;;; ;; ; ;;; ;;; ;; ; ;;; ;;; ;;; ;; ;;;; ;;; ;;; ;;
AC Parameters for Read Timing with Auto Precharge
T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK tCH tCL CKE tCKS tCMS tCMH Auto Precharge Start for Bank C tCKH /CS /RAS /CAS /WE BA0 BA1 A10 ADD tAS tAH DQM DQ L Hi-Z tRCD Activate Command for Bank C
Preliminary Data Sheet E1137E51 (Ver. 5.1)
;;;;
tAC tAC tAC tLZ tOH tOH tRAS tRRD tRC Read with Auto Precharge Command for Bank C Activate Command for Bank D
tAC
tHZ
tOH
tOH
Activate Command for Bank C
[Burst Length = 4, /CAS Latency = 3]
35
EDL1216CFBJ
;; ;;;; ;;;;;; ;; ;;;;; ; ;;;;;;; ;; ;;;;; ; ;;;;;; ;;;; ;; ;;;;; ;;;;; ; ; ;; ;;;; ;; ;;; ; ;;;;; ; ;;;; ; ; ; ;; ;; ;;;; ;;;; ;; ;; ;; ;;; ;; ;;
AC Parameters for Write Timing
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CKE /CS tCKS tCMS tCMH /RAS /CAS /WE BA0 BA1 A10 ADD tAS tAH DQM DQ L tDS tDH Hi-Z tRCD tRC tRRD tRCD tRAS tRC Write with Activate Auto Precharge Command Command for Bank B for Bank C Activate Command for Bank C
Preliminary Data Sheet E1137E51 (Ver. 5.1)
;; ;; ;; ;; ;; ;; ;;
Auto Precharge Start for Bank C
CLK
tCKH
tDAL
tDPL
tRP
Write Command for Bank B
Activate Precharge Command Command for Bank C for Bank B
Activate Command for Bank B
[Burst Length = 4]
36
EDL1216CFBJ
Mode Register Set
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;;;;;;;;;;; ;;;;;;;;;;; ;;;; ;;; ;;;;;;;;;;; ;;;;;;;;;;;; ;; ;;;;;;;;;;;; ;;;;;;;;;; ;;; ;; ;;;;;;;;;;;; ;;; ;;; ;;;;;;;;;;;;
CKE H tRSC
2 CLK (MIN.)
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADDRESS KEY
ADD
DQM
Hi-Z
DQ
Precharge All Banks Command
Mode Register Set Command
Activate Command is valid
tRP
Preliminary Data Sheet E1137E51 (Ver. 5.1)
37
EDL1216CFBJ
Extended Mode Register Set
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;;;;;;;;;;; ;;;;;;;;;;; ;;;; ;;; ;;;;;;;;;;; ;;;;;;;;;;;; ;; ;;;;;;;;;;;; ;;;;;;;;;; ;;; ;; ;;;;;;;;;;;; ;;; ;;; ;;;;;;;;;;;;
CKE H tRSC
2 CLK (MIN.)
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADDRESS KEY
ADD
DQM
Hi-Z
DQ
Precharge All Banks Command
Extended Mode Register Set Command
Activate Command is valid
tRP
;;;;;;;; ;; ;;;; ;;;; ;;;;;;;; ;; ;; ;; ;;;;;;;; ;; ;;;;;;;;;;;; ;; ;;;; ;;;;;;;;;;;; ;;;;; ;; ;; ;;;;;;;;;;; ;;;;;;;;;; ; ;; ;;; ;;
CLK Clock cycle is necessary High level is necessary CKE tRSC tRSC 2 refresh cycles are necessary /CS /RAS /CAS /WE BA0 BA1 A10 ADDRESS KEY ADDRESS KEY ADD DQM High level is necessary Hi-Z DQ Precharge All Banks Command is necessary tRP Mode Register Set Command is necessary Extended Mode Register Set Command is necessary CBR (Auto) Refresh Command is necessary tRC1 CBR (Auto) Refresh Command is necessary tRC1 Activate Command
Power On Sequence
Preliminary Data Sheet E1137E51 (Ver. 5.1)
38
EDL1216CFBJ
/CS Function Only /CS signal needs to be issued at minimum rate
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
CKE
H
/CS
/RAS
/CAS
/WE
BA0
L
BA1
L
A10
RAa
ADD
RAa
CAa
CAb
DQM
L Hi-Z
DQ
QAa1
QAa2 QAa3
QAa4
DAb1
DAb2
DAb3
DAb4
Activate Command for Bank A
Read Command for Bank A
Write Command for Bank A
Precharge Command for Bank A
[Burst Length = 4, /CAS Latency = 3]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
39
EDL1216CFBJ
Clock Suspension during Burst Read
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;;;;;;;;;;; ;; ;;;;;;;;;;; ;; ;; ;;;; ;;;;;;;;;;; ;;;;;;;;;;;;; ;; ;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;; ;;; ;;; ;; ;; ;;;;;;;;;; ;;;; ; ;; ;;;;;;;;;;
CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z DQ QAa1 QAa2 QAa3 QAa4 Activate Command for Bank A Read Command for Bank A 1-CLOCK SUSPENDED 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED Hi-Z (turn off) at the end of burst
[Burst Length = 4, /CAS Latency = 3]
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;;;;;;; ;;;;;;;;;;; ; ;;;;;;;;;;; ;;;;;;;;;;;; ; ;; ;;;;;;;;;;;; ;; ;; ;;;;;;;;;; ;;;;;;;;;;;; ;; ; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;
CLK CKE /CS /RAS /CAS /WE
BA0
BA1
A10
RAa
ADD
RAa
CAa
DQM
L
Hi-Z
DQ
QAa1
QAa2
QAa3
QAa4
Activate Command for Bank A
Read Command for Bank A
1-CLOCK SUSPENDED
2-CLOCK SUSPENDED
3-CLOCK Hi-Z (turn off) SUSPENDED at the end of burst
[Burst Length = 4, /CAS Latency = 2]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
40
EDL1216CFBJ
Clock Suspension during Burst Write
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;;;;;;;;;;; ;; ;;;;;;;;;;; ;; ;;;;;;;;;;;; ;;;;;;;;;;; ;;;; ;; ;;;;;;;;; ; ;;;;;;;;;;;;; ;;;;;;;;;;;; ;;; ;; ;; ;;; ;; ;;;;;;;;;; ;;; ;; ;;;;;;;;;; ;;;;;;; ;
CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z DQ DAa1 DAa2 DAa3 DAa4 Activate Command for Bank A Write 1-CLOCK Command SUSPENDED for Bank A 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED
Preliminary Data Sheet E1137E51 (Ver. 5.1)
41
EDL1216CFBJ
Power Down Mode and Clock Mask
;; ; ;;;;;;; ;;;; ;;;; ;;;;;;;;; ;; ; ; ;;;;;;;;; ;;; ;; ;; ;;;; ;;; ; ;;;;;;;;; ;; ;;;;;;;;; ;;; ;;;; ;;;; ;;;; ;;;;; ;;;; ;;;; ;;;;; ;;;; ;;;; ;;;;;;;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK tCKSP tCKSP CKE /CS VALID /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa DQM L Hi-Z DQ QAa1 QAa2 QAa3 QAa4 Activate Command for Bank A Power Down Mode Entry Read Command for Bank A Power Down Mode Exit Clock Mask Start Clock Mask End Precharge Command for Bank A Power Down Mode Entry PRECHARGE STANDBY Power Down Mode Exit ACTIVE STANDBY
[Burst Length = 4, /CAS Latency = 3]
;;;;;;;;;;; ;; ;;; ;; ;;;;;;;;;; ;;; ; ;;;; ;; ;;;; ;; ; ;;;;;;;;; ;; ;;;;;;;;; ; ;;; ;; ;;;;;;;; ;;;; ;;; ; ;;;;;;;; ;;;;;;;; ;;;;; ; ;;;; ;;; ;; ;;;;;;;; ;;;; ;;; ;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
CLK
tCKSP
tCKSP
CKE /CS
VALID
/RAS /CAS
/WE
BA0
BA1
A10
RAa
ADD
RAa
CAa
DQM
L
Hi-Z
DQ
QAa1 QAa2 QAa3
QAa4
Activate Command for Bank A Power Down Mode Entry
Read Command for Bank A Power Down Mode Exit Clock Mask Start Clock Mask End
Precharge Command for Bank A Power Down Mode Entry PRECHARGE STANDBY Power Down Mode Exit
ACTIVE STANDBY
[Burst Length = 4, /CAS Latency = 2]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
42
EDL1216CFBJ
Auto Refresh
T0 CLK
T1
T2
T3
T4
T5
T6
Tn
Tn + 1 Tn + 2
Tn + 3 Tn + 4 Tn + 5 Tn + 6
Tm
Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
;;; ;;;;;;; ;;;;;;;;;;; ;;;; ;;; ; ;; ;;;; ;;;; ;;;; ;;;;;; ;; ; ;;;; ;; ;;;;;;;;;;;; ;; ;;;;;;;;; ;; ;;;;;;;;; ;; ;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;
H L Hi-Z Q1 Precharge CBR (Auto) Refresh Command (if necessary) CBR (Auto) Refresh Activate Command Read Command tRP tRC1 tRC1
Preliminary Data Sheet E1137E51 (Ver. 5.1)
43
; ; ;;; ;;; ;;;;;; ;; ;;;;;;;;;;;; ;;;;;; ;; ; ;; ;; ;;; ;;;;;;;;;;; ;; ;; ;;;; ; ;; ; ;;;;;;;;;;; ;;;;;;;;;;; ;;; ;;;;;;;;;;; ;;;;;;;;;;; ;;;
Self Refresh (Entry and Exit)
T0 T1 T2 T3 T4 Tn Tn + 1 Tn + 2 Tm Tm + 1 Tk Tk + 1 Tk + 2 Tk + 3 Tk + 4 CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM L Hi-Z DQ Precharge Command (if necessary) Self Refresh Entry Self Refresh Exit Self Refresh Self Refresh Entry Exit (or Activate Command) Next Clock Enable tRP tRC2 tRC2 Activate Command Next Clock Enable
EDL1216CFBJ
Preliminary Data Sheet E1137E51 (Ver. 5.1)
44
EDL1216CFBJ
;;;;;;;;;;;; ;; ;;;;; ;; ;;; ;;;;;;;;;;;; ;;;;;;;;;;; ;;;;;;;;;;;; ;;;;; ;;;;; ; ;;;;;; ; ;; ;; ;; ; ;; ;;;;;; ;; ;;;;; ; ;;;; ;; ;; ;;;; ;;; ;; ;;;; ;;;;;;;; ;; ;;; ;; ;;;; ; ;;; ;;;;;;;;;;;; ;;
Random Column Read
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RAa ADD RAa CAa CAb CAc RAa CAa DQM L Hi-Z DQ QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 Activate Command for Bank A Read Command for Bank A Read Command for Bank A Read Command for Bank A Precharge Command for Bank A Activate Command for Bank A Read Command for Bank A
;;;;;;;;;;;;; ;;;;;;;;;; ;; ;; ;;;;;; ;; ;;; ;; ;;;;;;;;; ;;; ;; ;;; ;;;;;;;; ;;;;;; ;;; ;; ;; ;;; ;;;;; ;;;;;; ;;;;;;;;;;;; ;;;;;; ;;;;; ;; ;;;; ; ;;;;; ;;;; ;;;;;;; ;;;;;; ;;;;; ;;;;; ;;;;;;;;;;;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RAd ADD RAa CAa CAb CAc RAd CAd DQM L Hi-Z DQ QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 QAd1 QAd2 QAd3 Activate Command for Bank A Read Command for Bank A Read Command for Bank A Read Command for Bank A Precharge Command for Bank A Activate Command for Bank A Read Command for Bank A
[Burst Length = 4, /CAS Latency = 3]
[Burst Length = 4, /CAS Latency = 2]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
45
EDL1216CFBJ
;;;;;;;;;;;;; ;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;; ;;;;; ;;;;; ;;;;;; ;; ; ;; ;; ;;;;;; ;;;; ; ;;;; ;;;; ;;;; ;; ;; ; ;;;;;; ;; ;; ;; ;;;;;; ;; ;;;;; ;; ;; ;;;;; ;; ;; ;;; ;; ;;;;;;;;;;;; ;;;;;;;;;;;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RDa RDd ADD RDa CDa CDb CDc RDd CDd DQM L DQ Hi-Z DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 DDd1 DDd2 Activate Command for Bank D Write Command for Bank D Write Command for Bank D Write Command for Bank D Precharge Command for Bank D Activate Command for Bank D Write Command for Bank D
Random Column Write
[Burst Length = 4]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
46
EDL1216CFBJ
;;;;;;;;;;;; ;; ;;;;;;;; ;;; ;; ;;;; ;; ;;;;;;;;;;;; ;;; ;;;; ;; ;; ;;;; ;; ;;;;;;;; ; ; ;;; ;; ;;;;;; ;;;; ;; ;;;;;; ; ; ;; ;;;;; ;;;;; ; ;; ;; ;;; ;;; ; ;;;; ;; ;; ; ;; ;;;;;;;;;;;;; ;;;
Random Row Read
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RBa RAa RBb ADD RBa CBa RAa CAa RBb CBb DQM L DQ Hi-Z QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 Activate Command for Bank B Read Command for Bank B Activate Command for Bank A Read Command for Bank A Precharge Command for Bank B Activate Command for Bank B Read Command for Bank B Precharge Command for Bank A
;;;;;;;;;;;;; ;;;;;; ;; ;; ; ;;;; ; ;;;;;;;; ;; ;; ;;;;;;;; ;;;;;; ;; ;; ;; ;;;; ; ; ;; ;;; ;;; ;; ;;;;; ;;;; ;; ;;;;;; ;; ;;;;;;;; ;; ;; ;;;;;; ; ;;;;;;;;;;;; ;; ;;;;;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
[Burst Length = 8, /CAS Latency = 3]
CLK
CKE
H
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
RDa
RBa
RDb
ADD
RDa
CDa
RBa
CBa
RDb
CDb
DQM
L
DQ
Hi-Z
QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4
QBa5 QBa6 QBa7
QBa8
Activate Command for Bank D
Read Command for Bank D
Activate Command for Bank B
Read Command for Bank B Precharge Command for Bank D
Activate Command for Bank D
Read Command for Bank D
[Burst Length = 8, /CAS Latency = 2]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
47
EDL1216CFBJ
;;;;;;;;;;;; ;;;;;;;;;; ; ;; ;; ;;;;; ; ;;;;;;;;;;; ;; ;;;;;;;; ;;;;; ;; ;;;;;;;;;; ;; ;; ;;;; ;;; ;;;;;;;;;;; ;;; ;;;;; ;;; ; ;; ;; ;; ;;;; ;;;; ;;; ;;; ;;; ;; ;; ;;;;;;; ;;; ; ;;;;; ;; ;;;; ;; ;;
Random Row Write
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa RAb ADD RAa CAa RDa CDa RAb CAb DQM L DQ Hi-Z DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2 Activate Command for Bank A Write Command for Bank A Activate Command for Bank D Write Command for Bank D Precharge Command for Bank A Activate Command for Bank A Write Command for Bank A Precharge Command for Bank D
[Burst Length = 8]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
48
EDL1216CFBJ
Read and Write
T0
;;;;;;;;;;;;; ;;;; ;; ;;;; ;;;;;;;;;;;; ;;;; ;; ;;;; ;;;;;;;; ; ;;;;; ;;;; ;; ;;;;; ;;;; ;; ;;;;;;;; ;;; ;; ;;; ;;;;;;;;;;;; ;;; ; ;;;; ;;; ;;; ;; ;;;
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa CAb CAc Write Latency = 0 DQM L Word Masking DQ Hi-Z QAa1 QAa2 QAa3 QAa4 DAb1 DAb2 DAb4 QAc1 QAc2 Activate Command for Bank A Read Command for Bank A Write Command for Bank A Read Command for Bank A Hi-Z at the end of wrap function 0-Clock Latency 2-Clock Latency
[Burst Length = 4, /CAS Latency = 3]
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
; ;;;;;; ;;;;; ;;; ;;;;; ;;;;; ;;;;;; ;;;;; ; ;;; ; ; ;;;;; ;;;;; ;;; ;;;;;;;;;;;;; ;;;; ;; ;; ;;;;;;;;;;;;; ;; ;; ;;
CKE
H
CLK
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
ADD
RAa
CAa
CAb
CAc
Write Latency = 0
DQM
L
Word Masking
DQ
Hi-Z
QAa1 QAa2
QAa3 QAa4
DAb1
DAb2
DAb4
QAc1
QAc2
QAc4
Activate Command for Bank A
Read Command for Bank A
Write Command for Bank A
Read Command for Bank A
Hi-Z at the end of wrap function
0-Clock Latency
2-Clock Latency
[Burst Length = 4, /CAS Latency = 2]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
49
EDL1216CFBJ
Interleaved Column Read Cycle
T0 T1 T2 T3 T4
;;;;;;;;;;;; ;; ;;;;;;;;; ;;;;;;;;;;; ;;;;;; ;; ;;;;;;; ;;;; ;; ;;;;;;;; ;; ;;;;;;; ;; ;;;;;;;;; ;;;;;; ;; ;;;;;;; ;;; ;;;; ;;;; ;; ;;;; ;;; ;;; ;;; ;;;; ;; ;;;;;;;;;;;; ;;;;;;;;;;;;
T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa CDa CDb CDc CAb DQM L DQ Hi-Z Aa1 Aa2 Aa3 Aa4 Da1 Da2 Db1 Db2 Dc1 Dc2 Ab1 Ab2 Ab3 Ab4 Activate Command for Bank A Read Command for Bank A Activate Command for Bank D Read Command for Bank D Read Command for Bank D Read Command for Bank D Read Command for Bank A Precharge Command for Bank D Precharge Command for Bank A
[Burst Length = 4, /CAS Latency = 3]
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
;;;;;;;;; ;; ;;;; ;; ;;;;;;;;;; ;;;;;;;;;;; ;;;;;;;;;; ;;;;;;; ;; ;;; ; ;;;;;; ;;;; ;;;;;;;; ;;; ;; ;;;;;;;;;; ;;;;;;;;;; ;;;; ;;; ;;;;;
CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa ADD RAa CAa RDa CDa CDb CDc CAb CDd DQM L Hi-Z DQ Aa1 Aa2 Aa3 Aa4 Da1 Da2 Db1 Db2 Dc1 Dc2 Ab1 Ab2 Dd1 Dd2 Dd3 Dd4 Activate Command for Bank A Read Command for Bank A Activate Command for bank D Read Command for Bank D Read Command for Bank D Read Command for Bank D Read Command for Bank A Read Command for Bank D Precharge Command for Bank A Precharge Command for Bank D
[Burst Length = 4, /CAS Latency = 2]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
50
EDL1216CFBJ
Interleaved Column Write Cycle
T0 T1 T2 T3 T4
;;;;;;;;;;;; ;; ;;;;;;;;; ;;;;;;;;;;; ;;;;; ;; ;;; ;; ;; ;;;;;;; ;; ;;;;;;;;; ;; ;;;;;;;;; ;;;;;;;; ; ;;;;;;;; ;;; ;;;;; ; ;; ;;;;;;;; ; ;; ;;; ;; ;;;;; ;;;; ;; ;;;; ; ;; ;;;;;;;;;;;;
T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RBa ADD RAa CAa RBa CBa CBb CBc CAb CBd DQM L DQ Hi-Z Aa1 Aa2 Aa3 Aa4 Ba1 Ba2 Bb1 Bb2 Bc1 Bc2 Ab1 Ab2 Bd1 Bd2 Bd3 Activate Command for Bank A Write Command for Bank A Activate Command for Bank B Write Command for Bank B Write Command for Bank B Write Command for Bank B Write Command for Bank A Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B
Preliminary Data Sheet E1137E51 (Ver. 5.1)
51
; ;
Bd4
[Burst Length = 4]
EDL1216CFBJ
Auto Precharge after Read Burst
T0 T1 T2 T3 T4
;;;;;;;;;;;; ;;;;; ;;;;;; ;;; ;;;; ;; ;; ;;; ;; ;;;; ; ; ;;;;; ;;; ;; ;;; ;; ;;; ;;;;;;;; ;;; ;; ;;; ;; ; ;;;; ;;;;;; ;;;;;;;;;; ;;;;;;;;;;; ;;; ;; ;;;;;;;;;;;; ;;;;;;;;;;;;
T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RDa RDb ADD RAa CAa RDa CDa CAb RDb CDb DQM L DQ Hi-Z Activate Command for Bank A Activate Command for Bank D Read Command for Bank A Read with Auto Precharge Command for Bank D Read with Auto Precharge Command for Bank A Auto Precharge Start for Bank D Activate Command for Bank D Read with Auto Precharge Command for Bank D Auto Precharge Start for Bank A
[Burst Length = 4, /CAS Latency = 3]
;;;;;;;;;;; ;;;;;;;;;;;; ;;; ;;;;;;;;;; ;;;; ;;;;;; ;; ;; ; ;; ;; ;;;; ;;;;;; ;;;;;;;;;;; ;;;; ;;;;; ; ;;;;;;;; ;; ;;;;;;;;;; ;; ;; ;;; ;; ;;;;; ;;;;;; ; ;; ;; ;;; ;; ;; ;;; ;;;;;;;;;;;; ;;;;;;;;;;;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
CLK
CKE
H
/CS
/RAS /CAS
/WE
BA0
BA1
A10
RAa
RDa
RDb
RAc
ADD
RAa
CAa
RDa
CDa
CAb
RDb
CDb
RAc
CAc
DQM
L
DQ
Hi-Z
Activate Command for Bank A
Read Command for Bank A
Activate Command for Bank D
Read with Auto Precharge Command for Bank D
Activate Command Read with for Bank D Auto Precharge Command for Bank A Auto Precharge Start for Bank D
Activate Command Read with Read with for Bank A Auto Precharge Auto Precharge Command Command for Bank A for Bank D Auto Precharge Auto Precharge Start for Bank A Start for Bank D
[Burst Length = 4, /CAS Latency = 2]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
52
EDL1216CFBJ
Auto Precharge after Write Burst
T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
CKE
H
/CS
/RAS /CAS
/WE BA0
BA1
A10
RAa
RDa
RDb
ADD
RAa
CAa
RDa
CDa
CAb
RDb
CDb
DQM
L Hi-Z
DQ
Activate Command for Bank A
Activate Command for Bank D Write Command for Bank A Write with Auto Precharge Command for Bank D
Write with Auto Precharge Command for Bank A
Activate Command for bank D
Auto Precharge Start for Bank D
Write with Auto Precharge Command Auto Precharge for Bank D Start for Bank A
[Burst Length = 4]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
53
EDL1216CFBJ
Byte Operation
;; ;;; ;;;;;; ;;;;; ;;;;;; ;;;;; ;;;;;;;;;;;; ;;; ;; ;;; ;;;;;;;;;;;; ; ; ;;;;; ; ;; ; ; ;;;;;;;;;;;; ;;;;;; ;;;;; ;;; ;; ;; ; ;; ;;;;;; ;;;;; ;; ;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;; ;; ; ;; ;;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 ADD LDQM UDQM DQ (lower) DQ (upper) Activate Command for Bank D Read Command for Bank D Upper Byte not Read Lower Byte not Read Lower Byte not Write Upper Byte not Write Lower Byte not Write Read Command for Bank D Lower Byte not Read Lower Byte not Read
Preliminary Data Sheet E1137E51 (Ver. 5.1)
54
EDL1216CFBJ
Precharge Termination
T0 T1
;;;;;;;;;;;; ;;;;; ;; ;;; ;; ;;;; ;;; ;;; ;;;;; ;;;; ; ;; ;; ;;; ;;;;;;;;;; ;;;; ;;;; ;; ;; ;;; ; ; ; ;; ;; ;;;; ; ;;; ;; ;; ;; ;;;;;;;;;; ;;; ;; ;;;;; ; ;;; ;; ;;;;;;;;;;;; ;;;;;;;;;;;;; ;; ;;;;
T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RAb RAc ADD RAa CAa RAb CAb RAc DQM L Write Masking Hi-Z DQ DAa1 DAa2 DAa3 DAa4 DAa5 Hi-Z QAb1 QAb2 QAb3 QAb4 Activate Command for Bank A Write Command for Bank A PRE Termination of Burst tRCD tRAS tDPL Precharge Command for Bank A tRP Activate Command for Bank A Read Command for Bank A PRE Termination of Burst tRAS Precharge Command for Bank A Activate Command for Bank A
[Burst Length = 8, /CAS Latency = 3]
;;;;;;;;;;;; ;;;;;;; ;;; ;; ;;;;; ;; ;;;;;;; ;;; ;;;;;; ;;;;; ;;;;;;;;;;;; ;; ; ;;;; ;; ;;;;; ;;; ;;;;;;; ;;;; ;; ;;;;;; ;;;;;;;;; ;;;; ;; ;;;;; ;;;;;;;;;;;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa RAb RAc ADD RAa CAa RAb CAb RAc DQM L Write Masking DQ Hi-Z DAa1 DAa2 DAa3 DAa4 DAa5 QAb1 QAb2 QAb3 QAb4 QAb5 Hi-Z Activate Command for Bank A Write Command for Bank A PRE Termination of Burst tRCD tRAS tDPL Precharge Command for Bank A tRP Activate Command for Bank A Read Command for Bank A PRE Termination of Burst tRAS Precharge Command for Bank A Activate Command for Bank A
[Burst Length = 8, /CAS Latency = 2]
Preliminary Data Sheet E1137E51 (Ver. 5.1)
55
EDL1216CFBJ
Package Drawing
60-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
5.5 0.1
INDEX MARK
0.2 S A
6.0 0.1
0.2 S B
0.2 S
0.88 +0.12 -0.08
S
0.08 S
0.25 0.05
A
60-0.3 0.05
0.05 M S A B
INDEX MARK
1.25
4.5
0.5
0.25
4.5
B
0.5
ECA-TS2-0230-02
Preliminary Data Sheet E1137E51 (Ver. 5.1)
56
EDL1216CFBJ
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDL1216CFBJ. Type of Surface Mount Device EDL1216CFBJ: 60-ball FBGA < Lead free (Sn-Ag-Cu) >
Preliminary Data Sheet E1137E51 (Ver. 5.1)
57
EDL1216CFBJ
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E1137E51 (Ver. 5.1)
58
EDL1216CFBJ
Mobile RAM is a trademark of Elpida Memory, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0706
Preliminary Data Sheet E1137E51 (Ver. 5.1)
59

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